LAPIC Namespace Reference

Abstracts the local APIC (which is integrated into every CPU core) More...

Namespaces
namespace	IPI
	Inter-Processor Interrupts.
namespace	Timer
	Local Timer (for each LAPIC / CPU)

Classes
struct	SpuriousInterruptVectorRegister.__unnamed50__

Typedefs
typedef uint32_t	Register

Enumerations
enum	Model {   CLUSTER = 0x0 ,   FLAT = 0xf }
enum	APICSoftware {   APIC_DISABLED = 0 ,   APIC_ENABLED = 1 }
	APIC Software Status for Spurious Interrupt Vector. More...
enum	FocusProcessorChecking {   CHECKING_ENABLED = 0 ,   CHECKING_DISABLED = 1 }
	Focus Processor Checking for Spurious Interrupt Vector. More...
enum	SuppressEOIBroadcast {   BROADCAST = 0 ,   SUPPRESS_BROADCAST = 1 }
	Suppress End-Of-Interrupt-Broadcast for Spurious Interrupt Vector. More...
enum	Index : uint16_t {   IDENTIFICATION = 0x020 ,   VERSION = 0x030 ,   TASK_PRIORITY = 0x080 ,   EOI = 0x0b0 ,   LOGICAL_DESTINATION = 0x0d0 ,   DESTINATION_FORMAT = 0x0e0 ,   SPURIOUS_INTERRUPT_VECTOR = 0x0f0 ,   INTERRUPT_COMMAND_REGISTER_LOW = 0x300 ,   INTERRUPT_COMMAND_REGISTER_HIGH = 0x310 ,   TIMER_CONTROL = 0x320 ,   TIMER_INITIAL_COUNTER = 0x380 ,   TIMER_CURRENT_COUNTER = 0x390 ,   TIMER_DIVIDE_CONFIGURATION = 0x3e0 }
	Register Offset Index. More...

Functions
Register	read (Index idx)
	Get value from APIC register.
void	write (Index idx, Register value)
	Write value to APIC register.
uint8_t	getID ()
	Get the ID of the current core's LAPIC.
uint8_t	getLogicalID ()
	Get the Logical ID of the current core's LAPIC.
uint8_t	getVersion ()
	Get version number of local APIC.
void	init (uint8_t logical_id)
	Initialized the local APIC of the calling CPU core and sets the logical LAPIC ID in the LDR register.
void	endOfInterrupt ()
	Signalize EOI (End of interrupt)
void	setLogicalID (uint8_t id)
	Set the Logical ID of the current core's LAPIC.

Constants
volatile uintptr_t	base_address = 0xfee00000
	Base Address used with offset to access memory mapped registers.

Detailed Description

Abstracts the local APIC (which is integrated into every CPU core)

In modern (x86) PCs, every CPU core has its own Local APIC (LAPIC). The LAPIC is the link between the local CPU core and the I/O APIC (that takes care about external interrupt sources. Interrupt messages received by the LAPIC will be passed to the corresponding CPU core and trigger the interrupt handler on this core.

See also

ISDMv3 10.4 Local APIC

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Class Documentation

LAPIC::SpuriousInterruptVectorRegister.__unnamed50__

struct LAPIC::SpuriousInterruptVectorRegister.__unnamed50__

Class Members
uint32_t	spurious_vector: 8	Spurious Vector.
APICSoftware	apic_software: 1	APIC Software Enable/Disable.
FocusProcessorChecking	focus_processor_checking: 1	Focus Processor Checking.
uint32_t	reserved_1: 2
SuppressEOIBroadcast	eoi_broadcast_suppression: 1
uint32_t	reserved:19

Typedef Documentation

Register

typedef uint32_t LAPIC::Register

Enumeration Type Documentation

Model

enum LAPIC::Model

Enumerator
CLUSTER
FLAT

APICSoftware

enum LAPIC::APICSoftware

APIC Software Status for Spurious Interrupt Vector.

Enumerator
APIC_DISABLED
APIC_ENABLED

FocusProcessorChecking

enum LAPIC::FocusProcessorChecking

Focus Processor Checking for Spurious Interrupt Vector.

Enumerator
CHECKING_ENABLED
CHECKING_DISABLED

SuppressEOIBroadcast

enum LAPIC::SuppressEOIBroadcast

Suppress End-Of-Interrupt-Broadcast for Spurious Interrupt Vector.

Enumerator
BROADCAST
SUPPRESS_BROADCAST

Index

enum LAPIC::Index : uint16_t

Register Offset Index.

See also

ISDMv3 10.4.1 The Local APIC Block Diagram

Enumerator
IDENTIFICATION	Local APIC ID Register, RO (sometimes R/W). Do not change!
VERSION	Local APIC Version Register, RO.
TASK_PRIORITY	Task Priority Register, R/W.
EOI	EOI Register, WO.
LOGICAL_DESTINATION	Logical Destination Register, R/W.
DESTINATION_FORMAT	Destination Format Register, bits 0-27 RO, bits 28-31 R/W.
SPURIOUS_INTERRUPT_VECTOR	Spurious Interrupt Vector Register, bits 0-8 R/W, bits 9-1 R/W.
INTERRUPT_COMMAND_REGISTER_LOW	Interrupt Command Register 1, R/W.
INTERRUPT_COMMAND_REGISTER_HIGH	Interrupt Command Register 2, R/W.
TIMER_CONTROL	LAPIC timer control register, R/W.
TIMER_INITIAL_COUNTER	LAPIC timer initial counter register, R/W.
TIMER_CURRENT_COUNTER	LAPIC timer current counter register, RO.
TIMER_DIVIDE_CONFIGURATION	LAPIC timer divide configuration register, RW.

Function Documentation

read()

Register LAPIC::read

(

Index

idx

)

Get value from APIC register.

Parameters

idx	Register Offset Index

Returns

current value of register

write()

void LAPIC::write	(	Index	idx,
		Register	value
	)

Write value to APIC register.

Parameters

idx	Register Offset Index
value	value to be written into register

getID()

uint8_t LAPIC::getID

(

)

Get the ID of the current core's LAPIC.

Returns

LAPIC ID

getLogicalID()

uint8_t LAPIC::getLogicalID

(

)

Get the Logical ID of the current core's LAPIC.

Returns

Logical ID

getVersion()

uint8_t LAPIC::getVersion

(

)

Get version number of local APIC.

Returns

version number

init()

void LAPIC::init

(

uint8_t

logical_id

)

Initialized the local APIC of the calling CPU core and sets the logical LAPIC ID in the LDR register.

Parameters

logical_id

APIC ID to be set

endOfInterrupt()

void LAPIC::endOfInterrupt

(

)

Signalize EOI (End of interrupt)

Signalizes the LAPIC that the handling of the current interrupt finished. This function must be called at the end of interrupt handling before ireting.

setLogicalID()

void LAPIC::setLogicalID

(

uint8_t

id

)

Set the Logical ID of the current core's LAPIC.

Parameters

id	new Logical ID

Constant Documentation

base_address

volatile uintptr_t LAPIC::base_address = 0xfee00000

Base Address used with offset to access memory mapped registers.