StuBS
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Implements an abstraction for CPU internals. More...
Namespaces | |
namespace | Interrupt |
Exception and Interrupt control. | |
Classes | |
class | CR |
Access to the Control Register. More... | |
class | MSR |
Access to the Model-Specific Register (MSR) More... | |
Enumerations | |
enum | CR0 : uintptr_t { CR0_PE = 1U << 0 , CR0_MP = 1U << 1 , CR0_EM = 1U << 2 , CR0_TS = 1U << 3 , CR0_ET = 1U << 4 , CR0_NE = 1U << 5 , CR0_WP = 1U << 16 , CR0_AM = 1U << 18 , CR0_NW = 1U << 29 , CR0_CD = 1U << 30 , CR0_PG = 1U << 31 } |
Control Register 0. More... | |
enum | CR4 : uintptr_t { CR4_VME = 1U << 0 , CR4_PVI = 1U << 1 , CR4_TSD = 1U << 2 , CR4_DE = 1U << 3 , CR4_PSE = 1U << 4 , CR4_PAE = 1U << 5 , CR4_MCE = 1U << 6 , CR4_PGE = 1U << 7 , CR4_PCE = 1U << 8 , CR4_OSFXSR = 1U << 9 , CR4_OSXMMEXCPT = 1U << 10 , CR4_UMIP = 1U << 11 , CR4_VMXE = 1U << 13 , CR4_SMXE = 1U << 14 , CR4_FSGSBASE = 1U << 16 , CR4_PCIDE = 1U << 17 , CR4_OSXSAVE = 1U << 18 , CR4_SMEP = 1U << 20 , CR4_SMAP = 1U << 21 , CR4_PKE = 1U << 22 } |
Control Register 4. More... | |
enum | MSRs : uint32_t { MSR_PLATFORM_INFO = 0xceU , MSR_TSC_DEADLINE = 0x6e0U , MSR_EFER = 0xC0000080U , MSR_STAR = 0xC0000081U , MSR_LSTAR = 0xC0000082U , MSR_SFMASK = 0xC0000084U , MSR_FS_BASE = 0xC0000100U , MSR_GS_BASE = 0xC0000101U , MSR_SHADOW_GS_BASE = 0xC0000102U } |
Model-Specific Register Identifiers. More... | |
enum | MSR_EFER : uintptr_t { MSR_EFER_SCE = 1U << 0 , MSR_EFER_LME = 1U << 8 , MSR_EFER_LMA = 1U << 10 , MSR_EFER_NXE = 1U << 11 , MSR_EFER_SVME = 1U << 12 , MSR_EFER_LMSLE = 1U << 13 , MSR_EFER_FFXSR = 1U << 14 , MSR_EFER_TCE = 1U << 15 } |
Functions | |
void | init () |
Initialize this CPU core. | |
void | exit () |
Deinitialize this CPU core. | |
unsigned | getID () |
Get the ID of the current CPU core using LAPIC::getID() with an internal lookup table. | |
unsigned | count () |
Get number of available CPU cores. | |
unsigned | countOnline () |
Get number of successfully started (and currently active) CPU cores. | |
bool | isOnline (uint8_t core_id) |
Check if CPU core is currently active. | |
void | pause () |
Gives the core a hint that it is executing a spinloop and should sleep "shortly". | |
void | idle () |
Halt the CPU core until the next interrupt. | |
void | die () |
Permanently halts the core. | |
Constants | |
static unsigned | cores = 0 |
Number of available CPU cores. | |
static unsigned | core_id [255] |
Lookup table for CPU core IDs with LAPIC ID as index. | |
static unsigned | online_cores = 0 |
Number of currently online CPU cores. | |
static bool | online_core [Core::MAX] |
Lookup table for online CPU cores with CPU core ID as index. | |
const unsigned | MAX = 8 |
Maximum number of supported CPUs. | |
Implements an abstraction for CPU internals.
These internals include functions to allow or deny interrupts, access control registers.
Control Register 0.
Control Register 4.
enum Core::MSRs : uint32_t |
Model-Specific Register Identifiers.
Selection of useful identifiers.
Enumerator | |
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MSR_PLATFORM_INFO | Platform information including bus frequency (Intel) |
MSR_TSC_DEADLINE | Register for LAPIC::Timer Deadline mode. |
MSR_EFER | Extended Feature Enable Register,.
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MSR_STAR | eip (protected mode), ring 0 and 3 segment bases |
MSR_LSTAR | rip (long mode) |
MSR_SFMASK | lower 32 bit: flag mask, if bit is set corresponding rflag is cleared through syscall |
MSR_FS_BASE | |
MSR_GS_BASE | Current GS base pointer. |
MSR_SHADOW_GS_BASE | Usually called |
enum Core::MSR_EFER : uintptr_t |
void Core::init | ( | ) |
Initialize this CPU core.
Mark this core as online and setup the cores LAPIC by assigning it a unique logical APIC ID
void Core::exit | ( | ) |
Deinitialize this CPU core.
Mark this Core as offline
main()
or main_ap()
. unsigned Core::getID | ( | ) |
Get the ID of the current CPU core using LAPIC::getID() with an internal lookup table.
unsigned Core::count | ( | ) |
Get number of available CPU cores.
unsigned Core::countOnline | ( | ) |
Get number of successfully started (and currently active) CPU cores.
bool Core::isOnline | ( | uint8_t | core_id | ) |
Check if CPU core is currently active.
core_id | ID of the CPU core |
true
if successfully started and is currently active
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inline |
Gives the core a hint that it is executing a spinloop and should sleep "shortly".
Improves the over-all performance when executing a spinloop by waiting a short moment reduce the load on the memory.
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inline |
Halt the CPU core until the next interrupt.
Halts the current CPU core such that it will wake up on the next interrupt. Internally, this function first enables the interrupts via sti
and then halts the core using hlt
. Halted cores can only be woken by interrupts. The effect of sti
is delayed by one instruction, making the sequence sti hlt
atomic (if interrupts were disabled previously).
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inline |
Permanently halts the core.
Permanently halts the current CPU core. Internally, this function first disables the interrupts via cli
and then halts the CPU core using hlt
. As halted CPU cores can only be woken by interrupts, it is guaranteed that this core will be halted until the next reboot. The execution of die never returns. On multicore systems, only the executing CPU core will be halted permanently, other cores will continue execution.
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static |
Number of available CPU cores.
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static |
Lookup table for CPU core IDs with LAPIC ID as index.
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static |
Number of currently online CPU cores.
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static |
Lookup table for online CPU cores with CPU core ID as index.
const unsigned Core::MAX = 8 |
Maximum number of supported CPUs.