Core::Interrupt Namespace Reference

Exception and Interrupt control. More...

Enumerations
enum	Vector {   DIVISON_BY_ZERO = 0 ,   DEBUG = 1 ,   NON_MASKABLE_INTERRUPT = 2 ,   BREAKPOINT = 3 ,   OVERFLOW = 4 ,   BOUND_RANGE_EXCEEDED = 5 ,   INVALID_OPCODE = 6 ,   DEVICE_NOT_AVAILABLE = 7 ,   DOUBLE_FAULT = 8 ,   INVALID_TSS = 10 ,   SEGMENT_NOT_PRESENT = 11 ,   STACK_SEGMENT_FAULT = 12 ,   GENERAL_PROTECTION_FAULT = 13 ,   PAGE_FAULT = 14 ,   FLOATING_POINT_EXCEPTION = 16 ,   ALIGNMENT_CHECK = 17 ,   MACHINE_CHECK = 18 ,   SIMD_FP_EXCEPTION = 19 ,   EXCEPTIONS = 32 ,   TIMER = 32 ,   KEYBOARD = 33 ,   SERIAL = 34 ,   GDB = 35 ,   REALTIMECLOCK = 40 ,   HPET_TICKER = 41 ,   MOUSE = 44 ,   PANIC = 99 ,   ASSASSIN = 100 ,   WAKEUP = 101 ,   VECTORS = 256 }
	List of used interrupt vectors. More...

Functions
bool	isEnabled ()
	Check if interrupts are enabled on this CPU. More...
void	enable ()
	Allow interrupts. More...
bool	disable ()
	Forbid interrupts. More...
void	restore (bool val)
	Restore interrupt. More...

Constants
const uintptr_t	FLAG_ENABLE = 1 << 9
	Bit in FLAGS register corresponding to the current interrupt state.

Detailed Description

Exception and Interrupt control.

See also

ISDMv3, Chapter 6 Interrupt and Exception Handling

Enumeration Type Documentation

Vector

enum Core::Interrupt::Vector

List of used interrupt vectors.

The exception vectors from 0 to 31 are reserved for traps, faults and aborts. Their behavior is different for each exception, some push an error code, some are not recoverable.

The vectors from 32 to 255 are user defined interrupts.

See also

ISDMv3, 6.15 Exception and Interrupt Reference

Enumerator
DIVISON_BY_ZERO	Divide-by-zero Error (at a DIV/IDIV instruction)
DEBUG	Debug exception.
NON_MASKABLE_INTERRUPT	Non Maskable Interrupt.
BREAKPOINT	Breakpoint exception (used for debugging: GDB_Stub)
OVERFLOW	Overflow exception (at INTO instruction)
BOUND_RANGE_EXCEEDED	Bound Range Exceeded (at BOUND instruction)
INVALID_OPCODE	Opcode at Instruction Pointer is invalid (you probably shouldn't be here)
DEVICE_NOT_AVAILABLE	FPU/MMX/SSE instruction but corresponding extension not activate
DOUBLE_FAULT	Exception occurred while trying to call exception/interrupt handler.
INVALID_TSS	Invalid Task State Segment selector (see error code for index)
SEGMENT_NOT_PRESENT	Segment not available (see error code for selector index)
STACK_SEGMENT_FAULT	Stack segment not available or invalid (see error code for selector index)
GENERAL_PROTECTION_FAULT	Operation not allowed (see error code for selector index)
PAGE_FAULT	Operation on Page (r/w/x) not allowed for current privilege (error code + cr2)
FLOATING_POINT_EXCEPTION	x87 FPU error (at WAIT/FWAIT), accidentally Core::CR0_NE set?
ALIGNMENT_CHECK	Unaligned memory access in userspace (Exception activated by Core::CR0_AM)
MACHINE_CHECK	Model specific exception.
SIMD_FP_EXCEPTION	SSE/MMX error (if Core::CR4_OSXMMEXCPT activated)
EXCEPTIONS	Number of exceptions.
TIMER	Periodic CPU local LAPIC::Timer interrupt.
KEYBOARD	Keyboard interrupt (key press / release)
SERIAL	Receive interrupt of the Serial interface.
GDB	Inter-processor interrupt to stop other CPUs for debugging in GDB.
REALTIMECLOCK	RTC update or alert.
HPET_TICKER	Ticker timer interrupt (using HPET).
MOUSE	Mouse movement
PANIC	Panic interrupt to stop CPU (default value for IOAPIC devices)
ASSASSIN	Inter-processor interrupt to immediately stop threads running on other CPUs.
WAKEUP	Inter-processor interrupt to WakeUp sleeping CPUs.
VECTORS	Number of interrupt vectors.

Function Documentation

isEnabled()

bool Core::Interrupt::isEnabled ( )

inline

Check if interrupts are enabled on this CPU.

This is done by pushing the FLAGS register onto stack, reading it into a register and checking the corresponding bit.

Returns

true if enabled, false if disabled

enable()

void Core::Interrupt::enable ( )

inline

Allow interrupts.

Enables interrupt handling by executing the instruction sti. Since this instruction is delayed by one cycle, an subsequent nop is executed (to ensure deterministic behavior, independent from the compiler generated code)

A pending interrupt (i.e., those arriving while interrupts were disabled) will be delivered after re-enabling interrupts.

See also

ISDMv2, Chapter 4. STI - Set Interrupt Flag

disable()

bool Core::Interrupt::disable ( void  )

inline

Forbid interrupts.

Prevents interrupt handling by executing the instruction cli. Will return the previous interrupt state.

Returns

true if interrupts were enabled at the time of executing this function, false if they were already disabled.

See also

ISDMv2, Chapter 3. CLI - Ckear Interrupt Flag

restore()

void Core::Interrupt::restore ( bool  val )

inline

Restore interrupt.

Restore the interrupt state to the state prior to calling disable() by using its return value.

Note

This function will never disable interrupts, even if val is false! This function is designed to allow nested disabling and restoring of the interrupt state.

Parameters

val	if set to true, interrupts will be enabled; nothing will happen on false.