The High Precision Event Timer (HPET).
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namespace | HPET |
| Abstraction of the HPET existing in "modern" computers (since ~2005)
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enum | HPET::CounterSize {
SIZE_32BIT = 0x0
,
SIZE_64BIT = 0x1
} |
| Size of the global counter and the comparators.
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◆ HPET::Comparator::ConfigAndCapabilitiesRegister.__unnamed46__
struct HPET::Comparator::ConfigAndCapabilitiesRegister.__unnamed46__ |
Class Members |
uint64_t |
__pad0__: 1 |
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TriggerMode |
trigger_mode: 1 |
Generate edge or level triggered interrupts. |
uint64_t |
interrupt_status: 1 |
Enable (1 ) or disable (0 ) interrupts. |
ComparatorMode |
comparator_mode: 1 |
periodic or one shot mode |
uint64_t |
periodic_capable: 1 |
Is timer capable of periodic mode (read-only) |
CounterSize |
counter_size: 1 |
32- or 64bit size (read-only) |
uint64_t |
set_value: 1 |
if set to 1, the accumulator can be set in software |
uint64_t |
__pad1__: 1 |
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uint64_t |
small_mode: 1 |
if set to 1 while supporting 64bit size, the timer runs in 32-bit mode |
uint64_t |
ioapic_slot: 5 |
I/O-APIC slot (must be set in mask supported_ioapic_slots ) |
uint64_t |
fsb_interrupt_enabled: 1 |
if set to 1, the timer will use FSB interrupt mapping |
uint64_t |
fsb_interrupt_delivery: 1 |
if set to 1, the timer supports FSB interrupt mapping (read-only) |
uint64_t |
__pad2__: 16 |
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uint64_t |
supported_ioapic_slots: 32 |
bit mask containing the supported I/O APIC slots (read-only) |